mirror of
https://github.com/JoeyDeVries/LearnOpenGL.git
synced 2026-01-07 01:03:22 +08:00
Update GLM to latest version (0.9.9.3). This includes GLM's change of matrices no longer default initializing to the identity matrix. This commit thus also includes the update of all of LearnOpenGL's code to reflect this: all matrices are now constructor-initialized to the identity matrix where relevant.
This commit is contained in:
@@ -1,197 +1,169 @@
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
/// OpenGL Mathematics (glm.g-truc.net)
|
||||
///
|
||||
/// Copyright (c) 2005 - 2015 G-Truc Creation (www.g-truc.net)
|
||||
/// Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
/// of this software and associated documentation files (the "Software"), to deal
|
||||
/// in the Software without restriction, including without limitation the rights
|
||||
/// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
/// copies of the Software, and to permit persons to whom the Software is
|
||||
/// furnished to do so, subject to the following conditions:
|
||||
///
|
||||
/// The above copyright notice and this permission notice shall be included in
|
||||
/// all copies or substantial portions of the Software.
|
||||
///
|
||||
/// Restrictions:
|
||||
/// By making use of the Software for military purposes, you choose to make
|
||||
/// a Bunny unhappy.
|
||||
///
|
||||
/// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
/// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
/// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
/// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
/// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
/// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
/// THE SOFTWARE.
|
||||
///
|
||||
/// @ref gtc_bitfield
|
||||
/// @file glm/gtc/bitfield.inl
|
||||
/// @date 2011-10-14 / 2012-01-25
|
||||
/// @author Christophe Riccio
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "../simd/integer.h"
|
||||
|
||||
namespace glm{
|
||||
namespace detail
|
||||
{
|
||||
template <typename PARAM, typename RET>
|
||||
template<typename PARAM, typename RET>
|
||||
GLM_FUNC_DECL RET bitfieldInterleave(PARAM x, PARAM y);
|
||||
|
||||
template <typename PARAM, typename RET>
|
||||
template<typename PARAM, typename RET>
|
||||
GLM_FUNC_DECL RET bitfieldInterleave(PARAM x, PARAM y, PARAM z);
|
||||
|
||||
template <typename PARAM, typename RET>
|
||||
template<typename PARAM, typename RET>
|
||||
GLM_FUNC_DECL RET bitfieldInterleave(PARAM x, PARAM y, PARAM z, PARAM w);
|
||||
|
||||
template <>
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint16 bitfieldInterleave(glm::uint8 x, glm::uint8 y)
|
||||
{
|
||||
glm::uint16 REG1(x);
|
||||
glm::uint16 REG2(y);
|
||||
|
||||
REG1 = ((REG1 << 4) | REG1) & glm::uint16(0x0F0F);
|
||||
REG2 = ((REG2 << 4) | REG2) & glm::uint16(0x0F0F);
|
||||
REG1 = ((REG1 << 4) | REG1) & static_cast<glm::uint16>(0x0F0F);
|
||||
REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint16>(0x0F0F);
|
||||
|
||||
REG1 = ((REG1 << 2) | REG1) & glm::uint16(0x3333);
|
||||
REG2 = ((REG2 << 2) | REG2) & glm::uint16(0x3333);
|
||||
REG1 = ((REG1 << 2) | REG1) & static_cast<glm::uint16>(0x3333);
|
||||
REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint16>(0x3333);
|
||||
|
||||
REG1 = ((REG1 << 1) | REG1) & glm::uint16(0x5555);
|
||||
REG2 = ((REG2 << 1) | REG2) & glm::uint16(0x5555);
|
||||
REG1 = ((REG1 << 1) | REG1) & static_cast<glm::uint16>(0x5555);
|
||||
REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint16>(0x5555);
|
||||
|
||||
return REG1 | (REG2 << 1);
|
||||
return REG1 | static_cast<glm::uint16>(REG2 << 1);
|
||||
}
|
||||
|
||||
template <>
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(glm::uint16 x, glm::uint16 y)
|
||||
{
|
||||
glm::uint32 REG1(x);
|
||||
glm::uint32 REG2(y);
|
||||
|
||||
REG1 = ((REG1 << 8) | REG1) & glm::uint32(0x00FF00FF);
|
||||
REG2 = ((REG2 << 8) | REG2) & glm::uint32(0x00FF00FF);
|
||||
REG1 = ((REG1 << 8) | REG1) & static_cast<glm::uint32>(0x00FF00FF);
|
||||
REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint32>(0x00FF00FF);
|
||||
|
||||
REG1 = ((REG1 << 4) | REG1) & glm::uint32(0x0F0F0F0F);
|
||||
REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x0F0F0F0F);
|
||||
REG1 = ((REG1 << 4) | REG1) & static_cast<glm::uint32>(0x0F0F0F0F);
|
||||
REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint32>(0x0F0F0F0F);
|
||||
|
||||
REG1 = ((REG1 << 2) | REG1) & glm::uint32(0x33333333);
|
||||
REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x33333333);
|
||||
REG1 = ((REG1 << 2) | REG1) & static_cast<glm::uint32>(0x33333333);
|
||||
REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint32>(0x33333333);
|
||||
|
||||
REG1 = ((REG1 << 1) | REG1) & glm::uint32(0x55555555);
|
||||
REG2 = ((REG2 << 1) | REG2) & glm::uint32(0x55555555);
|
||||
REG1 = ((REG1 << 1) | REG1) & static_cast<glm::uint32>(0x55555555);
|
||||
REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint32>(0x55555555);
|
||||
|
||||
return REG1 | (REG2 << 1);
|
||||
}
|
||||
|
||||
template <>
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint32 x, glm::uint32 y)
|
||||
{
|
||||
glm::uint64 REG1(x);
|
||||
glm::uint64 REG2(y);
|
||||
|
||||
REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x0000FFFF0000FFFF);
|
||||
REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x0000FFFF0000FFFF);
|
||||
REG1 = ((REG1 << 16) | REG1) & static_cast<glm::uint64>(0x0000FFFF0000FFFFull);
|
||||
REG2 = ((REG2 << 16) | REG2) & static_cast<glm::uint64>(0x0000FFFF0000FFFFull);
|
||||
|
||||
REG1 = ((REG1 << 8) | REG1) & glm::uint64(0x00FF00FF00FF00FF);
|
||||
REG2 = ((REG2 << 8) | REG2) & glm::uint64(0x00FF00FF00FF00FF);
|
||||
REG1 = ((REG1 << 8) | REG1) & static_cast<glm::uint64>(0x00FF00FF00FF00FFull);
|
||||
REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint64>(0x00FF00FF00FF00FFull);
|
||||
|
||||
REG1 = ((REG1 << 4) | REG1) & glm::uint64(0x0F0F0F0F0F0F0F0F);
|
||||
REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x0F0F0F0F0F0F0F0F);
|
||||
REG1 = ((REG1 << 4) | REG1) & static_cast<glm::uint64>(0x0F0F0F0F0F0F0F0Full);
|
||||
REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint64>(0x0F0F0F0F0F0F0F0Full);
|
||||
|
||||
REG1 = ((REG1 << 2) | REG1) & glm::uint64(0x3333333333333333);
|
||||
REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x3333333333333333);
|
||||
REG1 = ((REG1 << 2) | REG1) & static_cast<glm::uint64>(0x3333333333333333ull);
|
||||
REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint64>(0x3333333333333333ull);
|
||||
|
||||
REG1 = ((REG1 << 1) | REG1) & glm::uint64(0x5555555555555555);
|
||||
REG2 = ((REG2 << 1) | REG2) & glm::uint64(0x5555555555555555);
|
||||
REG1 = ((REG1 << 1) | REG1) & static_cast<glm::uint64>(0x5555555555555555ull);
|
||||
REG2 = ((REG2 << 1) | REG2) & static_cast<glm::uint64>(0x5555555555555555ull);
|
||||
|
||||
return REG1 | (REG2 << 1);
|
||||
}
|
||||
|
||||
template <>
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(glm::uint8 x, glm::uint8 y, glm::uint8 z)
|
||||
{
|
||||
glm::uint32 REG1(x);
|
||||
glm::uint32 REG2(y);
|
||||
glm::uint32 REG3(z);
|
||||
|
||||
REG1 = ((REG1 << 16) | REG1) & glm::uint32(0x00FF0000FF0000FF);
|
||||
REG2 = ((REG2 << 16) | REG2) & glm::uint32(0x00FF0000FF0000FF);
|
||||
REG3 = ((REG3 << 16) | REG3) & glm::uint32(0x00FF0000FF0000FF);
|
||||
REG1 = ((REG1 << 16) | REG1) & static_cast<glm::uint32>(0xFF0000FFu);
|
||||
REG2 = ((REG2 << 16) | REG2) & static_cast<glm::uint32>(0xFF0000FFu);
|
||||
REG3 = ((REG3 << 16) | REG3) & static_cast<glm::uint32>(0xFF0000FFu);
|
||||
|
||||
REG1 = ((REG1 << 8) | REG1) & glm::uint32(0xF00F00F00F00F00F);
|
||||
REG2 = ((REG2 << 8) | REG2) & glm::uint32(0xF00F00F00F00F00F);
|
||||
REG3 = ((REG3 << 8) | REG3) & glm::uint32(0xF00F00F00F00F00F);
|
||||
REG1 = ((REG1 << 8) | REG1) & static_cast<glm::uint32>(0x0F00F00Fu);
|
||||
REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint32>(0x0F00F00Fu);
|
||||
REG3 = ((REG3 << 8) | REG3) & static_cast<glm::uint32>(0x0F00F00Fu);
|
||||
|
||||
REG1 = ((REG1 << 4) | REG1) & glm::uint32(0x30C30C30C30C30C3);
|
||||
REG2 = ((REG2 << 4) | REG2) & glm::uint32(0x30C30C30C30C30C3);
|
||||
REG3 = ((REG3 << 4) | REG3) & glm::uint32(0x30C30C30C30C30C3);
|
||||
REG1 = ((REG1 << 4) | REG1) & static_cast<glm::uint32>(0xC30C30C3u);
|
||||
REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint32>(0xC30C30C3u);
|
||||
REG3 = ((REG3 << 4) | REG3) & static_cast<glm::uint32>(0xC30C30C3u);
|
||||
|
||||
REG1 = ((REG1 << 2) | REG1) & glm::uint32(0x9249249249249249);
|
||||
REG2 = ((REG2 << 2) | REG2) & glm::uint32(0x9249249249249249);
|
||||
REG3 = ((REG3 << 2) | REG3) & glm::uint32(0x9249249249249249);
|
||||
REG1 = ((REG1 << 2) | REG1) & static_cast<glm::uint32>(0x49249249u);
|
||||
REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint32>(0x49249249u);
|
||||
REG3 = ((REG3 << 2) | REG3) & static_cast<glm::uint32>(0x49249249u);
|
||||
|
||||
return REG1 | (REG2 << 1) | (REG3 << 2);
|
||||
}
|
||||
|
||||
template <>
|
||||
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint16 x, glm::uint16 y, glm::uint16 z)
|
||||
{
|
||||
glm::uint64 REG1(x);
|
||||
glm::uint64 REG2(y);
|
||||
glm::uint64 REG3(z);
|
||||
|
||||
REG1 = ((REG1 << 32) | REG1) & glm::uint64(0xFFFF00000000FFFFull);
|
||||
REG2 = ((REG2 << 32) | REG2) & glm::uint64(0xFFFF00000000FFFFull);
|
||||
REG3 = ((REG3 << 32) | REG3) & glm::uint64(0xFFFF00000000FFFFull);
|
||||
REG1 = ((REG1 << 32) | REG1) & static_cast<glm::uint64>(0xFFFF00000000FFFFull);
|
||||
REG2 = ((REG2 << 32) | REG2) & static_cast<glm::uint64>(0xFFFF00000000FFFFull);
|
||||
REG3 = ((REG3 << 32) | REG3) & static_cast<glm::uint64>(0xFFFF00000000FFFFull);
|
||||
|
||||
REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x00FF0000FF0000FFull);
|
||||
REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x00FF0000FF0000FFull);
|
||||
REG3 = ((REG3 << 16) | REG3) & glm::uint64(0x00FF0000FF0000FFull);
|
||||
REG1 = ((REG1 << 16) | REG1) & static_cast<glm::uint64>(0x00FF0000FF0000FFull);
|
||||
REG2 = ((REG2 << 16) | REG2) & static_cast<glm::uint64>(0x00FF0000FF0000FFull);
|
||||
REG3 = ((REG3 << 16) | REG3) & static_cast<glm::uint64>(0x00FF0000FF0000FFull);
|
||||
|
||||
REG1 = ((REG1 << 8) | REG1) & glm::uint64(0xF00F00F00F00F00Full);
|
||||
REG2 = ((REG2 << 8) | REG2) & glm::uint64(0xF00F00F00F00F00Full);
|
||||
REG3 = ((REG3 << 8) | REG3) & glm::uint64(0xF00F00F00F00F00Full);
|
||||
REG1 = ((REG1 << 8) | REG1) & static_cast<glm::uint64>(0xF00F00F00F00F00Full);
|
||||
REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint64>(0xF00F00F00F00F00Full);
|
||||
REG3 = ((REG3 << 8) | REG3) & static_cast<glm::uint64>(0xF00F00F00F00F00Full);
|
||||
|
||||
REG1 = ((REG1 << 4) | REG1) & glm::uint64(0x30C30C30C30C30C3ull);
|
||||
REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x30C30C30C30C30C3ull);
|
||||
REG3 = ((REG3 << 4) | REG3) & glm::uint64(0x30C30C30C30C30C3ull);
|
||||
REG1 = ((REG1 << 4) | REG1) & static_cast<glm::uint64>(0x30C30C30C30C30C3ull);
|
||||
REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint64>(0x30C30C30C30C30C3ull);
|
||||
REG3 = ((REG3 << 4) | REG3) & static_cast<glm::uint64>(0x30C30C30C30C30C3ull);
|
||||
|
||||
REG1 = ((REG1 << 2) | REG1) & glm::uint64(0x9249249249249249ull);
|
||||
REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x9249249249249249ull);
|
||||
REG3 = ((REG3 << 2) | REG3) & glm::uint64(0x9249249249249249ull);
|
||||
REG1 = ((REG1 << 2) | REG1) & static_cast<glm::uint64>(0x9249249249249249ull);
|
||||
REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint64>(0x9249249249249249ull);
|
||||
REG3 = ((REG3 << 2) | REG3) & static_cast<glm::uint64>(0x9249249249249249ull);
|
||||
|
||||
return REG1 | (REG2 << 1) | (REG3 << 2);
|
||||
}
|
||||
|
||||
template <>
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint32 x, glm::uint32 y, glm::uint32 z)
|
||||
{
|
||||
glm::uint64 REG1(x);
|
||||
glm::uint64 REG2(y);
|
||||
glm::uint64 REG3(z);
|
||||
|
||||
REG1 = ((REG1 << 32) | REG1) & glm::uint64(0xFFFF00000000FFFFull);
|
||||
REG2 = ((REG2 << 32) | REG2) & glm::uint64(0xFFFF00000000FFFFull);
|
||||
REG3 = ((REG3 << 32) | REG3) & glm::uint64(0xFFFF00000000FFFFull);
|
||||
REG1 = ((REG1 << 32) | REG1) & static_cast<glm::uint64>(0xFFFF00000000FFFFull);
|
||||
REG2 = ((REG2 << 32) | REG2) & static_cast<glm::uint64>(0xFFFF00000000FFFFull);
|
||||
REG3 = ((REG3 << 32) | REG3) & static_cast<glm::uint64>(0xFFFF00000000FFFFull);
|
||||
|
||||
REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x00FF0000FF0000FFull);
|
||||
REG2 = ((REG2 << 16) | REG2) & glm::uint64(0x00FF0000FF0000FFull);
|
||||
REG3 = ((REG3 << 16) | REG3) & glm::uint64(0x00FF0000FF0000FFull);
|
||||
REG1 = ((REG1 << 16) | REG1) & static_cast<glm::uint64>(0x00FF0000FF0000FFull);
|
||||
REG2 = ((REG2 << 16) | REG2) & static_cast<glm::uint64>(0x00FF0000FF0000FFull);
|
||||
REG3 = ((REG3 << 16) | REG3) & static_cast<glm::uint64>(0x00FF0000FF0000FFull);
|
||||
|
||||
REG1 = ((REG1 << 8) | REG1) & glm::uint64(0xF00F00F00F00F00Full);
|
||||
REG2 = ((REG2 << 8) | REG2) & glm::uint64(0xF00F00F00F00F00Full);
|
||||
REG3 = ((REG3 << 8) | REG3) & glm::uint64(0xF00F00F00F00F00Full);
|
||||
REG1 = ((REG1 << 8) | REG1) & static_cast<glm::uint64>(0xF00F00F00F00F00Full);
|
||||
REG2 = ((REG2 << 8) | REG2) & static_cast<glm::uint64>(0xF00F00F00F00F00Full);
|
||||
REG3 = ((REG3 << 8) | REG3) & static_cast<glm::uint64>(0xF00F00F00F00F00Full);
|
||||
|
||||
REG1 = ((REG1 << 4) | REG1) & glm::uint64(0x30C30C30C30C30C3ull);
|
||||
REG2 = ((REG2 << 4) | REG2) & glm::uint64(0x30C30C30C30C30C3ull);
|
||||
REG3 = ((REG3 << 4) | REG3) & glm::uint64(0x30C30C30C30C30C3ull);
|
||||
REG1 = ((REG1 << 4) | REG1) & static_cast<glm::uint64>(0x30C30C30C30C30C3ull);
|
||||
REG2 = ((REG2 << 4) | REG2) & static_cast<glm::uint64>(0x30C30C30C30C30C3ull);
|
||||
REG3 = ((REG3 << 4) | REG3) & static_cast<glm::uint64>(0x30C30C30C30C30C3ull);
|
||||
|
||||
REG1 = ((REG1 << 2) | REG1) & glm::uint64(0x9249249249249249ull);
|
||||
REG2 = ((REG2 << 2) | REG2) & glm::uint64(0x9249249249249249ull);
|
||||
REG3 = ((REG3 << 2) | REG3) & glm::uint64(0x9249249249249249ull);
|
||||
REG1 = ((REG1 << 2) | REG1) & static_cast<glm::uint64>(0x9249249249249249ull);
|
||||
REG2 = ((REG2 << 2) | REG2) & static_cast<glm::uint64>(0x9249249249249249ull);
|
||||
REG3 = ((REG3 << 2) | REG3) & static_cast<glm::uint64>(0x9249249249249249ull);
|
||||
|
||||
return REG1 | (REG2 << 1) | (REG3 << 2);
|
||||
}
|
||||
|
||||
template <>
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(glm::uint8 x, glm::uint8 y, glm::uint8 z, glm::uint8 w)
|
||||
{
|
||||
glm::uint32 REG1(x);
|
||||
@@ -199,25 +171,25 @@ namespace detail
|
||||
glm::uint32 REG3(z);
|
||||
glm::uint32 REG4(w);
|
||||
|
||||
REG1 = ((REG1 << 12) | REG1) & glm::uint32(0x000F000F000F000F);
|
||||
REG2 = ((REG2 << 12) | REG2) & glm::uint32(0x000F000F000F000F);
|
||||
REG3 = ((REG3 << 12) | REG3) & glm::uint32(0x000F000F000F000F);
|
||||
REG4 = ((REG4 << 12) | REG4) & glm::uint32(0x000F000F000F000F);
|
||||
REG1 = ((REG1 << 12) | REG1) & static_cast<glm::uint32>(0x000F000Fu);
|
||||
REG2 = ((REG2 << 12) | REG2) & static_cast<glm::uint32>(0x000F000Fu);
|
||||
REG3 = ((REG3 << 12) | REG3) & static_cast<glm::uint32>(0x000F000Fu);
|
||||
REG4 = ((REG4 << 12) | REG4) & static_cast<glm::uint32>(0x000F000Fu);
|
||||
|
||||
REG1 = ((REG1 << 6) | REG1) & glm::uint32(0x0303030303030303);
|
||||
REG2 = ((REG2 << 6) | REG2) & glm::uint32(0x0303030303030303);
|
||||
REG3 = ((REG3 << 6) | REG3) & glm::uint32(0x0303030303030303);
|
||||
REG4 = ((REG4 << 6) | REG4) & glm::uint32(0x0303030303030303);
|
||||
REG1 = ((REG1 << 6) | REG1) & static_cast<glm::uint32>(0x03030303u);
|
||||
REG2 = ((REG2 << 6) | REG2) & static_cast<glm::uint32>(0x03030303u);
|
||||
REG3 = ((REG3 << 6) | REG3) & static_cast<glm::uint32>(0x03030303u);
|
||||
REG4 = ((REG4 << 6) | REG4) & static_cast<glm::uint32>(0x03030303u);
|
||||
|
||||
REG1 = ((REG1 << 3) | REG1) & glm::uint32(0x1111111111111111);
|
||||
REG2 = ((REG2 << 3) | REG2) & glm::uint32(0x1111111111111111);
|
||||
REG3 = ((REG3 << 3) | REG3) & glm::uint32(0x1111111111111111);
|
||||
REG4 = ((REG4 << 3) | REG4) & glm::uint32(0x1111111111111111);
|
||||
REG1 = ((REG1 << 3) | REG1) & static_cast<glm::uint32>(0x11111111u);
|
||||
REG2 = ((REG2 << 3) | REG2) & static_cast<glm::uint32>(0x11111111u);
|
||||
REG3 = ((REG3 << 3) | REG3) & static_cast<glm::uint32>(0x11111111u);
|
||||
REG4 = ((REG4 << 3) | REG4) & static_cast<glm::uint32>(0x11111111u);
|
||||
|
||||
return REG1 | (REG2 << 1) | (REG3 << 2) | (REG4 << 3);
|
||||
}
|
||||
|
||||
template <>
|
||||
template<>
|
||||
GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(glm::uint16 x, glm::uint16 y, glm::uint16 z, glm::uint16 w)
|
||||
{
|
||||
glm::uint64 REG1(x);
|
||||
@@ -225,31 +197,31 @@ namespace detail
|
||||
glm::uint64 REG3(z);
|
||||
glm::uint64 REG4(w);
|
||||
|
||||
REG1 = ((REG1 << 24) | REG1) & glm::uint64(0x000000FF000000FFull);
|
||||
REG2 = ((REG2 << 24) | REG2) & glm::uint64(0x000000FF000000FFull);
|
||||
REG3 = ((REG3 << 24) | REG3) & glm::uint64(0x000000FF000000FFull);
|
||||
REG4 = ((REG4 << 24) | REG4) & glm::uint64(0x000000FF000000FFull);
|
||||
REG1 = ((REG1 << 24) | REG1) & static_cast<glm::uint64>(0x000000FF000000FFull);
|
||||
REG2 = ((REG2 << 24) | REG2) & static_cast<glm::uint64>(0x000000FF000000FFull);
|
||||
REG3 = ((REG3 << 24) | REG3) & static_cast<glm::uint64>(0x000000FF000000FFull);
|
||||
REG4 = ((REG4 << 24) | REG4) & static_cast<glm::uint64>(0x000000FF000000FFull);
|
||||
|
||||
REG1 = ((REG1 << 12) | REG1) & glm::uint64(0x000F000F000F000Full);
|
||||
REG2 = ((REG2 << 12) | REG2) & glm::uint64(0x000F000F000F000Full);
|
||||
REG3 = ((REG3 << 12) | REG3) & glm::uint64(0x000F000F000F000Full);
|
||||
REG4 = ((REG4 << 12) | REG4) & glm::uint64(0x000F000F000F000Full);
|
||||
REG1 = ((REG1 << 12) | REG1) & static_cast<glm::uint64>(0x000F000F000F000Full);
|
||||
REG2 = ((REG2 << 12) | REG2) & static_cast<glm::uint64>(0x000F000F000F000Full);
|
||||
REG3 = ((REG3 << 12) | REG3) & static_cast<glm::uint64>(0x000F000F000F000Full);
|
||||
REG4 = ((REG4 << 12) | REG4) & static_cast<glm::uint64>(0x000F000F000F000Full);
|
||||
|
||||
REG1 = ((REG1 << 6) | REG1) & glm::uint64(0x0303030303030303ull);
|
||||
REG2 = ((REG2 << 6) | REG2) & glm::uint64(0x0303030303030303ull);
|
||||
REG3 = ((REG3 << 6) | REG3) & glm::uint64(0x0303030303030303ull);
|
||||
REG4 = ((REG4 << 6) | REG4) & glm::uint64(0x0303030303030303ull);
|
||||
REG1 = ((REG1 << 6) | REG1) & static_cast<glm::uint64>(0x0303030303030303ull);
|
||||
REG2 = ((REG2 << 6) | REG2) & static_cast<glm::uint64>(0x0303030303030303ull);
|
||||
REG3 = ((REG3 << 6) | REG3) & static_cast<glm::uint64>(0x0303030303030303ull);
|
||||
REG4 = ((REG4 << 6) | REG4) & static_cast<glm::uint64>(0x0303030303030303ull);
|
||||
|
||||
REG1 = ((REG1 << 3) | REG1) & glm::uint64(0x1111111111111111ull);
|
||||
REG2 = ((REG2 << 3) | REG2) & glm::uint64(0x1111111111111111ull);
|
||||
REG3 = ((REG3 << 3) | REG3) & glm::uint64(0x1111111111111111ull);
|
||||
REG4 = ((REG4 << 3) | REG4) & glm::uint64(0x1111111111111111ull);
|
||||
REG1 = ((REG1 << 3) | REG1) & static_cast<glm::uint64>(0x1111111111111111ull);
|
||||
REG2 = ((REG2 << 3) | REG2) & static_cast<glm::uint64>(0x1111111111111111ull);
|
||||
REG3 = ((REG3 << 3) | REG3) & static_cast<glm::uint64>(0x1111111111111111ull);
|
||||
REG4 = ((REG4 << 3) | REG4) & static_cast<glm::uint64>(0x1111111111111111ull);
|
||||
|
||||
return REG1 | (REG2 << 1) | (REG3 << 2) | (REG4 << 3);
|
||||
}
|
||||
}//namespace detail
|
||||
|
||||
template <typename genIUType>
|
||||
template<typename genIUType>
|
||||
GLM_FUNC_QUALIFIER genIUType mask(genIUType Bits)
|
||||
{
|
||||
GLM_STATIC_ASSERT(std::numeric_limits<genIUType>::is_integer, "'mask' accepts only integer values");
|
||||
@@ -257,15 +229,15 @@ namespace detail
|
||||
return Bits >= sizeof(genIUType) * 8 ? ~static_cast<genIUType>(0) : (static_cast<genIUType>(1) << Bits) - static_cast<genIUType>(1);
|
||||
}
|
||||
|
||||
template <typename T, precision P, template <typename, precision> class vecIUType>
|
||||
GLM_FUNC_QUALIFIER vecIUType<T, P> mask(vecIUType<T, P> const & v)
|
||||
template<length_t L, typename T, qualifier Q>
|
||||
GLM_FUNC_QUALIFIER vec<L, T, Q> mask(vec<L, T, Q> const& v)
|
||||
{
|
||||
GLM_STATIC_ASSERT(std::numeric_limits<T>::is_integer, "'mask' accepts only integer values");
|
||||
|
||||
return detail::functor1<T, T, P, vecIUType>::call(mask, v);
|
||||
return detail::functor1<vec, L, T, T, Q>::call(mask, v);
|
||||
}
|
||||
|
||||
template <typename genIType>
|
||||
template<typename genIType>
|
||||
GLM_FUNC_QUALIFIER genIType bitfieldRotateRight(genIType In, int Shift)
|
||||
{
|
||||
GLM_STATIC_ASSERT(std::numeric_limits<genIType>::is_integer, "'bitfieldRotateRight' accepts only integer values");
|
||||
@@ -274,8 +246,8 @@ namespace detail
|
||||
return (In << static_cast<genIType>(Shift)) | (In >> static_cast<genIType>(BitSize - Shift));
|
||||
}
|
||||
|
||||
template <typename T, precision P, template <typename, precision> class vecType>
|
||||
GLM_FUNC_QUALIFIER vecType<T, P> bitfieldRotateRight(vecType<T, P> const & In, int Shift)
|
||||
template<length_t L, typename T, qualifier Q>
|
||||
GLM_FUNC_QUALIFIER vec<L, T, Q> bitfieldRotateRight(vec<L, T, Q> const& In, int Shift)
|
||||
{
|
||||
GLM_STATIC_ASSERT(std::numeric_limits<T>::is_integer, "'bitfieldRotateRight' accepts only integer values");
|
||||
|
||||
@@ -283,7 +255,7 @@ namespace detail
|
||||
return (In << static_cast<T>(Shift)) | (In >> static_cast<T>(BitSize - Shift));
|
||||
}
|
||||
|
||||
template <typename genIType>
|
||||
template<typename genIType>
|
||||
GLM_FUNC_QUALIFIER genIType bitfieldRotateLeft(genIType In, int Shift)
|
||||
{
|
||||
GLM_STATIC_ASSERT(std::numeric_limits<genIType>::is_integer, "'bitfieldRotateLeft' accepts only integer values");
|
||||
@@ -292,8 +264,8 @@ namespace detail
|
||||
return (In >> static_cast<genIType>(Shift)) | (In << static_cast<genIType>(BitSize - Shift));
|
||||
}
|
||||
|
||||
template <typename T, precision P, template <typename, precision> class vecType>
|
||||
GLM_FUNC_QUALIFIER vecType<T, P> bitfieldRotateLeft(vecType<T, P> const & In, int Shift)
|
||||
template<length_t L, typename T, qualifier Q>
|
||||
GLM_FUNC_QUALIFIER vec<L, T, Q> bitfieldRotateLeft(vec<L, T, Q> const& In, int Shift)
|
||||
{
|
||||
GLM_STATIC_ASSERT(std::numeric_limits<T>::is_integer, "'bitfieldRotateLeft' accepts only integer values");
|
||||
|
||||
@@ -301,26 +273,26 @@ namespace detail
|
||||
return (In >> static_cast<T>(Shift)) | (In << static_cast<T>(BitSize - Shift));
|
||||
}
|
||||
|
||||
template <typename genIUType>
|
||||
template<typename genIUType>
|
||||
GLM_FUNC_QUALIFIER genIUType bitfieldFillOne(genIUType Value, int FirstBit, int BitCount)
|
||||
{
|
||||
return Value | static_cast<genIUType>(mask(BitCount) << FirstBit);
|
||||
}
|
||||
|
||||
template <typename T, precision P, template <typename, precision> class vecType>
|
||||
GLM_FUNC_QUALIFIER vecType<T, P> bitfieldFillOne(vecType<T, P> const & Value, int FirstBit, int BitCount)
|
||||
template<length_t L, typename T, qualifier Q>
|
||||
GLM_FUNC_QUALIFIER vec<L, T, Q> bitfieldFillOne(vec<L, T, Q> const& Value, int FirstBit, int BitCount)
|
||||
{
|
||||
return Value | static_cast<T>(mask(BitCount) << FirstBit);
|
||||
}
|
||||
|
||||
template <typename genIUType>
|
||||
template<typename genIUType>
|
||||
GLM_FUNC_QUALIFIER genIUType bitfieldFillZero(genIUType Value, int FirstBit, int BitCount)
|
||||
{
|
||||
return Value & static_cast<genIUType>(~(mask(BitCount) << FirstBit));
|
||||
}
|
||||
|
||||
template <typename T, precision P, template <typename, precision> class vecType>
|
||||
GLM_FUNC_QUALIFIER vecType<T, P> bitfieldFillZero(vecType<T, P> const & Value, int FirstBit, int BitCount)
|
||||
template<length_t L, typename T, qualifier Q>
|
||||
GLM_FUNC_QUALIFIER vec<L, T, Q> bitfieldFillZero(vec<L, T, Q> const& Value, int FirstBit, int BitCount)
|
||||
{
|
||||
return Value & static_cast<T>(~(mask(BitCount) << FirstBit));
|
||||
}
|
||||
@@ -351,6 +323,34 @@ namespace detail
|
||||
return detail::bitfieldInterleave<uint8, uint16>(x, y);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER uint16 bitfieldInterleave(u8vec2 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint8, uint16>(v.x, v.y);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER u8vec2 bitfieldDeinterleave(glm::uint16 x)
|
||||
{
|
||||
uint16 REG1(x);
|
||||
uint16 REG2(x >>= 1);
|
||||
|
||||
REG1 = REG1 & static_cast<uint16>(0x5555);
|
||||
REG2 = REG2 & static_cast<uint16>(0x5555);
|
||||
|
||||
REG1 = ((REG1 >> 1) | REG1) & static_cast<uint16>(0x3333);
|
||||
REG2 = ((REG2 >> 1) | REG2) & static_cast<uint16>(0x3333);
|
||||
|
||||
REG1 = ((REG1 >> 2) | REG1) & static_cast<uint16>(0x0F0F);
|
||||
REG2 = ((REG2 >> 2) | REG2) & static_cast<uint16>(0x0F0F);
|
||||
|
||||
REG1 = ((REG1 >> 4) | REG1) & static_cast<uint16>(0x00FF);
|
||||
REG2 = ((REG2 >> 4) | REG2) & static_cast<uint16>(0x00FF);
|
||||
|
||||
REG1 = ((REG1 >> 8) | REG1) & static_cast<uint16>(0xFFFF);
|
||||
REG2 = ((REG2 >> 8) | REG2) & static_cast<uint16>(0xFFFF);
|
||||
|
||||
return glm::u8vec2(REG1, REG2);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER int32 bitfieldInterleave(int16 x, int16 y)
|
||||
{
|
||||
union sign16
|
||||
@@ -377,6 +377,34 @@ namespace detail
|
||||
return detail::bitfieldInterleave<uint16, uint32>(x, y);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER glm::uint32 bitfieldInterleave(u16vec2 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint16, uint32>(v.x, v.y);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER glm::u16vec2 bitfieldDeinterleave(glm::uint32 x)
|
||||
{
|
||||
glm::uint32 REG1(x);
|
||||
glm::uint32 REG2(x >>= 1);
|
||||
|
||||
REG1 = REG1 & static_cast<glm::uint32>(0x55555555);
|
||||
REG2 = REG2 & static_cast<glm::uint32>(0x55555555);
|
||||
|
||||
REG1 = ((REG1 >> 1) | REG1) & static_cast<glm::uint32>(0x33333333);
|
||||
REG2 = ((REG2 >> 1) | REG2) & static_cast<glm::uint32>(0x33333333);
|
||||
|
||||
REG1 = ((REG1 >> 2) | REG1) & static_cast<glm::uint32>(0x0F0F0F0F);
|
||||
REG2 = ((REG2 >> 2) | REG2) & static_cast<glm::uint32>(0x0F0F0F0F);
|
||||
|
||||
REG1 = ((REG1 >> 4) | REG1) & static_cast<glm::uint32>(0x00FF00FF);
|
||||
REG2 = ((REG2 >> 4) | REG2) & static_cast<glm::uint32>(0x00FF00FF);
|
||||
|
||||
REG1 = ((REG1 >> 8) | REG1) & static_cast<glm::uint32>(0x0000FFFF);
|
||||
REG2 = ((REG2 >> 8) | REG2) & static_cast<glm::uint32>(0x0000FFFF);
|
||||
|
||||
return glm::u16vec2(REG1, REG2);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER int64 bitfieldInterleave(int32 x, int32 y)
|
||||
{
|
||||
union sign32
|
||||
@@ -403,6 +431,37 @@ namespace detail
|
||||
return detail::bitfieldInterleave<uint32, uint64>(x, y);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER glm::uint64 bitfieldInterleave(u32vec2 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint32, uint64>(v.x, v.y);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER glm::u32vec2 bitfieldDeinterleave(glm::uint64 x)
|
||||
{
|
||||
glm::uint64 REG1(x);
|
||||
glm::uint64 REG2(x >>= 1);
|
||||
|
||||
REG1 = REG1 & static_cast<glm::uint64>(0x5555555555555555ull);
|
||||
REG2 = REG2 & static_cast<glm::uint64>(0x5555555555555555ull);
|
||||
|
||||
REG1 = ((REG1 >> 1) | REG1) & static_cast<glm::uint64>(0x3333333333333333ull);
|
||||
REG2 = ((REG2 >> 1) | REG2) & static_cast<glm::uint64>(0x3333333333333333ull);
|
||||
|
||||
REG1 = ((REG1 >> 2) | REG1) & static_cast<glm::uint64>(0x0F0F0F0F0F0F0F0Full);
|
||||
REG2 = ((REG2 >> 2) | REG2) & static_cast<glm::uint64>(0x0F0F0F0F0F0F0F0Full);
|
||||
|
||||
REG1 = ((REG1 >> 4) | REG1) & static_cast<glm::uint64>(0x00FF00FF00FF00FFull);
|
||||
REG2 = ((REG2 >> 4) | REG2) & static_cast<glm::uint64>(0x00FF00FF00FF00FFull);
|
||||
|
||||
REG1 = ((REG1 >> 8) | REG1) & static_cast<glm::uint64>(0x0000FFFF0000FFFFull);
|
||||
REG2 = ((REG2 >> 8) | REG2) & static_cast<glm::uint64>(0x0000FFFF0000FFFFull);
|
||||
|
||||
REG1 = ((REG1 >> 16) | REG1) & static_cast<glm::uint64>(0x00000000FFFFFFFFull);
|
||||
REG2 = ((REG2 >> 16) | REG2) & static_cast<glm::uint64>(0x00000000FFFFFFFFull);
|
||||
|
||||
return glm::u32vec2(REG1, REG2);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER int32 bitfieldInterleave(int8 x, int8 y, int8 z)
|
||||
{
|
||||
union sign8
|
||||
@@ -430,6 +489,11 @@ namespace detail
|
||||
return detail::bitfieldInterleave<uint8, uint32>(x, y, z);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER uint32 bitfieldInterleave(u8vec3 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint8, uint32>(v.x, v.y, v.z);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER int64 bitfieldInterleave(int16 x, int16 y, int16 z)
|
||||
{
|
||||
union sign16
|
||||
@@ -457,6 +521,11 @@ namespace detail
|
||||
return detail::bitfieldInterleave<uint32, uint64>(x, y, z);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER uint64 bitfieldInterleave(u16vec3 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint32, uint64>(v.x, v.y, v.z);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER int64 bitfieldInterleave(int32 x, int32 y, int32 z)
|
||||
{
|
||||
union sign16
|
||||
@@ -484,6 +553,11 @@ namespace detail
|
||||
return detail::bitfieldInterleave<uint32, uint64>(x, y, z);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER uint64 bitfieldInterleave(u32vec3 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint32, uint64>(v.x, v.y, v.z);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER int32 bitfieldInterleave(int8 x, int8 y, int8 z, int8 w)
|
||||
{
|
||||
union sign8
|
||||
@@ -512,6 +586,11 @@ namespace detail
|
||||
return detail::bitfieldInterleave<uint8, uint32>(x, y, z, w);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER uint32 bitfieldInterleave(u8vec4 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint8, uint32>(v.x, v.y, v.z, v.w);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER int64 bitfieldInterleave(int16 x, int16 y, int16 z, int16 w)
|
||||
{
|
||||
union sign16
|
||||
@@ -539,4 +618,9 @@ namespace detail
|
||||
{
|
||||
return detail::bitfieldInterleave<uint16, uint64>(x, y, z, w);
|
||||
}
|
||||
|
||||
GLM_FUNC_QUALIFIER uint64 bitfieldInterleave(u16vec4 const& v)
|
||||
{
|
||||
return detail::bitfieldInterleave<uint16, uint64>(v.x, v.y, v.z, v.w);
|
||||
}
|
||||
}//namespace glm
|
||||
|
||||
Reference in New Issue
Block a user